Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, chip area with was often enlarged, and in turn cost also increased. To effectively improve immunity without enlarging area, circuit methods therefore invented. An overview on methodology used prevent issues integrated circuits (ICs) is presented this article. The solutions, including reducing I/O pad trigger current, sensing current control power supply, restarting supply through an MOS switch shut off are overviewed.